← 研踪 PaperTrailarXiv:2611.04019 · v1
qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
首次提交 2026-11-03 06:01
版本更新 2026-11-03 06:01
雷达观测 2026-11-04 23:40
摘要
Rapid Single Flux Quantum (RSFQ) logic can operate at ultra-high clock frequencies; however, its physical design is complicated by explicit splitter trees and deep gate-level pipelines in which every logic gate is clocked. To address this challenge, we present qLevelPlace, a level-based placement framework for RSFQ circuits. We separate gate and splitter placement into two stages to better support levelguided gate-to-row assignment and use a timing-aware quadratic cost function to penalize long interconnects. Experiments on the benchmark circuits show that, on average, qLevelPlace achieves a $2.65\times$ higher clock frequency and a 51% reduction in layout area compared with the state-of-the-art RSFQ placer qPlace.
作者备注：7 pages, 4 figures. Accepted to ASP-DAC 2027
观测到的版本
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v1 · 2026-11-03 06:01 · 最新观测版本
qLevelPlace: A Level-Based Placement Framework for RSFQ Circuits
Rapid Single Flux Quantum (RSFQ) logic can operate at ultra-high clock frequencies; however, its physical design is complicated by explicit splitter trees and deep gate-level pipelines in which every logic gate is clocked. To address this challenge, we present qLevelPlace, a level-based placement framework for RSFQ circuits. We separate gate and splitter placement into two stages to better support levelguided gate-to-row assignment and use a timing-aware quadratic cost function to penalize long interconnects. Experiments on the benchmark circuits show that, on average, qLevelPlace achieves a $2.65\times$ higher clock frequency and a 51% reduction in layout area compared with the state-of-the-art RSFQ placer qPlace.
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