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arXiv:2611.16363 · v1

Vector-Space Projection and Unified Complex-Valued Acceleration for Scaling Matrix-Based Brain-Inspired Representations

首次提交 2026-11-12 14:25
版本更新 2026-11-12 14:25
雷达观测 2026-11-13 14:15
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摘要

Symbolic reasoning at scale requires representations that are both expressive and hardware-efficient. Hyperdimensional Computing (HDC) provides a promising brain-inspired framework, encoding concepts as high-dimensional vectors composed through efficient algebraic operations. However, the widely used Fourier Holographic Reduced Representation (FHRR) relies on commutative binding, which cannot encode order or directionality. Prior FPGA/ASIC accelerators recover this through costly permutation logic, incurring irregular memory access and high control overhead. Generalized Holographic Reduced Representations (GHRR) instead redefine binding as non-commutative matrix multiplication, naturally encoding sequences, graphs, and hierarchies without permutations-but at the cost of turning every element into a matrix, introducing compute and storage overhead that limits scalability. In this work, we propose a flattening methodology that preserves GHRR's matrix-based encoding while executing training and inference directly in vector space, functionally equivalent to FHRR inference yet free of permutation logic. We further design a custom 28 nm ASIC that fuses binding and similarity into a unified complex-valued datapath, with dual-DMA streaming and runtime normalization for accurate inference. Against a PyTorch baseline on an NVIDIA RTX 4090 GPU, the prototype delivers 1.36x-1.56x higher throughput and 16.2x-18.6x better energy efficiency.

作者备注:7 pages. Published at ISLPED 2026

期刊信息:Proc. ACM/IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2026, Article 24, pp. 1-7

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v1 · 2026-11-12 14:25 · 最新观测版本

Vector-Space Projection and Unified Complex-Valued Acceleration for Scaling Matrix-Based Brain-Inspired Representations

Symbolic reasoning at scale requires representations that are both expressive and hardware-efficient. Hyperdimensional Computing (HDC) provides a promising brain-inspired framework, encoding concepts as high-dimensional vectors composed through efficient algebraic operations. However, the widely used Fourier Holographic Reduced Representation (FHRR) relies on commutative binding, which cannot encode order or directionality. Prior FPGA/ASIC accelerators recover this through costly permutation logic, incurring irregular memory access and high control overhead. Generalized Holographic Reduced Representations (GHRR) instead redefine binding as non-commutative matrix multiplication, naturally encoding sequences, graphs, and hierarchies without permutations-but at the cost of turning every element into a matrix, introducing compute and storage overhead that limits scalability. In this work, we propose a flattening methodology that preserves GHRR's matrix-based encoding while executing training and inference directly in vector space, functionally equivalent to FHRR inference yet free of permutation logic. We further design a custom 28 nm ASIC that fuses binding and similarity into a unified complex-valued datapath, with dual-DMA streaming and runtime normalization for accurate inference. Against a PyTorch baseline on an NVIDIA RTX 4090 GPU, the prototype delivers 1.36x-1.56x higher throughput and 16.2x-18.6x better energy efficiency.

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