Recent generations of high bandwidth memory (HBM), such as HBM4, allow the base die of the memory stack to be manufactured using a logic process that can accommodate more complex controller functions next to the DRAM. We present the first systematic quantitative study of function-level controller placement between the host and the HBM4 base die on a silicon interposer. We divide the controller into its main functions and evaluate four placements, from a complete host controller to a complete base die controller, with intermediate placements that move maintenance or scheduling to the base die. We extend Ramulator 2 with HBM4 timing and maintenance, model a die-to-die (D2D) link with timing checks at the DRAM interface, and compose area, energy, and temperature from synthesized controller blocks, modeled storage, and interface data. A provisioned D2D link preserves per-stack bandwidth and adds about twice its one-way delay to unloaded latency. Maintenance moves to the base die with no bandwidth cost and frees host command slots, and the freed share grows with stack height. Replacing the wide interface with a D2D link saves 61% of host shoreline and 16.85 mm2 of host area per stack. The D2D link dominates the added base die area and power, and the base die runs cooler under streaming with link energy below 0.4 pJ/bit. Shared control delivers up to 1.72x the throughput of static partitioning between two requestors.
Speculative decoding efficiency depends on the number of consecutively accepted draft tokens, yet token-level training objectives do not directly optimize this quantity. We introduce D-REAL (Drafter Reinforcement of Expected Acceptance Length), a post-training method that directly optimizes expected acceptance length for a fixed decoding context. D-REAL weights position-wise draft-target distributional overlap by prefix survival probabilities along a draft-sampled prefix, faithfully capturing the sequential dependence of verification on earlier proposals. By accounting for the parameter dependence of the proposal distribution, we derive an unbiased gradient estimator for this single-round objective under stochastic verification. We evaluate D-REAL on DSpark and DFlash2 with Qwen3-8B as the target model across ten benchmarks. Starting from baselines whose mean acceptance length has plateaued, one epoch of D-REAL post-training consistently improves the benchmark-averaged mean acceptance length by up to 0.23 tokens across both architectures under greedy (T = 0.0) and stochastic (T = 1.0) sampling, translating into up to a 9.4% end-to-end serving throughput improvement.