使用高层次 Vitis HLS 实现 AWS 云 FPGA 开发
Enabling AWS Cloud FPGA Development Using High-Level Vitis HLS
David Rostcheck
AI 速览：作者提出一套从高层次语言到 AWS EC2 F2 云 FPGA 的 Vitis HLS 工具链与四级调试方法，并以 TinyBERT 地址命名实体识别模型的部分层实现作为验证案例。
We present a toolchain for development of ML models on AWS EC2 F2 cloud FPGA infrastructure from high-level language, implementing a complete Vitis HLS to HDK bridge to AFI workflow that has been absent from the academic literature despite eight years of AWS FPGA availability. We introduce a four-level methodology (FP32 PyTorch, bit-accurate quantized Python, HLS C-simulation, physical FPGA) to aid in localizing errors, including FPGA-specific circuit errors. Together these tools allow coding agents to effectively implement FPGA designs from user directions, testing and debugging as needed. We document the deployment workflow, timing closure strategies, and practical HLS engineering decisions that proved crucial. We validate using TinyBERT fine-tuned for address Named Entity Recognition, implementing the embedding layer and the first of four encoder layers on the FPGA hardware. Our implementation streams weights from host DRAM, yielding poor performance compared to CPU/GPU implementations; we discuss forward paths.