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原文摘要

Near-Threshold Computing (NTC) offers a substan- tial energy savings, i.e., up to 10x, for digital circuits. However, due to Process, Voltage, and Temperature (PVT) variations, low voltage operating digital processors face increased susceptibility to timing errors. This work equips conventional massive MIMO algorithms with computational error detection mechanisms, en- abling reliable operation down to near-threshold voltages. While conventional hardware based Timing Error Detection (TED) systems introduce substantial overhead, this work modifies MIMO algorithms to seamlessly integrate low overhead Algorithm Based Fault Tolerance (ABFT). A co-simulation framework combining transistor level SPICE simulations and workload aware fault injection is developed to investigate reliability, Bit Error Rate (BER), energy savings, and overheads of modified algorithms operating at low voltages. The transistor-level characterization was performed in PSpice using generic Level-1 Shichman-Hodges CMOS transistor models with Monte Carlo parameter variations. No specific CMOS fabrication process node was assumed. Conse- quently, the reported energy savings are analytical estimates and are not specific to a particular CMOS fabrication technology. We evaluate Gauss Seidel (GS), ADMM based infinity norm detection (ADMIN), and Conjugate Gradient (CG) detectors using circuit derived fault models. Results demonstrate remarkable algorith- mic resilience. Although undetected computational errors in some trials near the Point of First Failure (PoFF) were observed, BER increases by only 0.7% to 1.4%, while beyond PoFF, ABFT reported nearly all erroneous cases. The proposed checksum based ABFT detects most arithmetic and memory errors, with an estimated overhead below 2% for a 64 x 16 MIMO system, decreasing further for larger configurations.