The increasing demand for real-time processing and personalized deep learning has made edge-device training essential but challenging due to high memory and computational costs. To address this, we propose a Convolutional Neural Network (CNN) training accelerator with a dynamic sparse update mechanism that selectively updates important parameters using a random channel strategy, avoiding costly evaluations. Combined with activation pruning, our approach reduces activation storage to just 3.4\% of the original. Our hardware features a fused forward dataflow that concurrently processes group normalization and convolution, reducing training time by 45\% through computation reordering and efficient zero-skipping. Implemented in TSMC 28nm at FP8 precision, the design operates at 800 MHz, achieving 8 TOPS peak throughput, 31.13 TOPS/W energy efficiency, and 14.8 TOPS/mm$^2$ area efficiency, with power consumption ranging from 257 to 272 mW. The design enables on-device training within a sub-100KB on-chip SRAM budget (95KB in silicon).
Autoregressive large language model (LLM) inference is often limited by external-memory bandwidth, while existing ultra-low-bit trellis quantization reconstructs floating-point weights and leaves runtime Hadamard-transform and decoder costs unresolved. This paper presents TQIR, an algorithm--hardware co-design that decouples storage precision ($S$) from decoded-weight ($W$) and activation ($A$) compute precisions, enabling a better accuracy--hardware trade-off. TQIR performs trellis matching with floating-point candidates offline while constraining each candidate to an INT8 or INT4 codeword that can be reproduced exactly for integer GEMM at runtime. To reduce transform cost while preserving the integer weight path, TQIR relocates the reverse Hadamard transform to the activation side and employs an $H_{128}$ Subspace Hadamard Transform, together with a subspace-aligned $128\times2$ trellis tile that preserves the original 256-weight sequence length. The configurable decoder, synthesized in a TSMC 16-nm process, delivers 307.2~Gweights/s in 0.0509~mm$^2$ and achieves 13.93$\times$ and 1.52$\times$ the normalized decoder-area efficiency of Ecco and Codeword Decomposition, respectively. These results show that fixed-rate trellis compression can reduce weight traffic while sustaining an integer-GEMM datapath matched to the evaluated memory and PE rates.