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新论文 · v1arXiv:2611.11475

CU-3D: A Scalable Legality-Aware RTL-to-GDS Flow for 3D-IC Physical Design

Mingjun Wang, Guanqi Li, Yihan Wen, Lancheng Zou, Mingjun Li, Feng Gu, Fengrui Liu, Jianan Mu 等 13 位作者

原文摘要

Face-to-face (F2F) hybrid bonds shorten interdie connections, but data, clock, and power-grid (PG) connections must be realized together. CU-3D is a RTL-to-GDS physical design flow based on commercial EDA tools. It derives role-compatible hybrid-bond (HB) sites from a 17-metal ASAP7-based technology model, complete HB footprints, and constructed PG geometry. To coordinate partitioning with placement flexibility, Scaled refines an inherited 2D placement, whereas Fresh places the receiving die first and uses its pin locations and clock loads to guide placement of the other die. Data and clock HB assignments are jointly optimized while retaining alternative data sites and reserving capacity for subsequent PG assignment. The selected HB sites and stacks are preserved during 3D clock-tree synthesis, supply-aware cell insertion, and routing. Across eleven designs, including a 133-macro processor, the flow achieves zero backend DRC violations and passes signal-connectivity checks. Nine paired designs admit lower-footprint, lower-power implementations; four improve setup WNS. On JPEG, early joint planning gains 87 ps and mobility-aware partitioning gains 346 ps. Path analysis explains why cell-delay savings can outweigh net-delay increases.

cs.AR

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arXiv ↗PDF ↗
版本更新 · v2arXiv:2601.19912

Analysis of LLM Vulnerability to GPU Soft Errors: An Instruction-Level Fault Injection Study

Duo Chai, Zizhen Liu, Shuhuai Wang, Songwei Pei, Cheng Liu, Huawei Li, Shangguang Wang

原文摘要

Large language models (LLMs) are highly compute- and memory-intensive, posing significant demands on high-performance GPUs. At the same time, advances in GPU technology driven by shrinking transistor sizes and lower operating voltages have made these devices increasingly susceptible to soft errors, particularly in radiation-prone environments such as satellite computing scenarios. While prior work has examined GPU soft errors, most studies have focused on general-purpose applications or conventional neural networks primarily used for vision tasks such as classification and detection. However, vulnerability analysis of modern LLMs remains limited, despite their rapid adoption in diverse application scenarios. Given the unique characteristics of LLMs, their resilience to soft errors may differ substantially from earlier models. To bridge this gap, we conduct the first instruction-level fault injection study of LLM inference to analyze the factors affecting LLM vulnerability. Our approach reveals reliability characteristics from multiple perspectives, highlighting the effects of model architecture, parameter scale, and task complexity. These findings provide new insights into LLM reliability and inform the design of more effective fault tolerance mechanisms.

cs.AR · cs.AI · cs.CR

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arXiv ↗PDF ↗
首次观测 · 记录 #1ACL Anthology · ACL 2026:acl:2026.acl-long.1154ACL Anthology · ACL 2026

ChipSeek: Optimizing Verilog Generation via EDA-Integrated Reinforcement Learning

Zhirong Chen, Kaiyan Chang Institute of Computing Technology, CAS, Zhuolin Li Peking University, Cangyuan Li , Chinese Academy of Sciences, Xinyang He, Chujie Chen, Mengdi Wang, Haobo Xu 等 11 位作者

原文摘要

Large Language Models have emerged as powerful tools for automating Register-Transfer Level (RTL) code generation, yet they face critical limitations: existing approaches typically fail to simultaneously optimize functional correctness and hardware efficiency metrics such as Power, Performance, and Area (PPA). Methods relying on supervised fine-tuning commonly produce functionally correct but suboptimal designs due to the lack of inherent mechanisms for learning hardware optimization principles. Conversely, external post-processing techniques aiming to refine PPA performance after generation often suffer from inefficiency and do not improve the LLMs’ intrinsic capabilities.To overcome these challenges, we propose ChipSeek, a novel hierarchical reward based reinforcement learning framework designed to encourage LLMs to generate RTL code that is both functionally correct and optimized for PPA metrics. Our approach integrates direct feedback from EDA simulators and synthesis tools into a hierarchical reward mechanism, facilitating a nuanced understanding of hardware design trade-offs. Through Curriculum-Guided Dynamic Policy Optimization (CDPO), ChipSeek enhances the LLM’s ability to generate high-quality, optimized RTL code. Evaluations on standard benchmarks demonstrate ChipSeek’s superior performance, achieving state-of-the-art functional correctness and PPA performance. Furthermore, it excels in specific optimization tasks, consistently yielding highly efficient designs when individually targeting fine-grained optimization goals such as power, delay, and area. The artifact is open-source in https://github.com/rong-hash/chipseek.

cs.CL

Proceedings of the 64th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers) · 2026 · 正式发表