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原文摘要

Probabilistic-bit (p-bit) invertible logic encodes a Boolean relation as an energy whose ground states are its legal assignments, computing in any direction by sampling. Traditional constructions target ground-state membership and a wide minimum energy gap, yet finite-time samplers traverse excited states. We cast Hamiltonian design as inverse statistical mechanics: fit an energy with interactions up to order four whose Gibbs law approaches uniformity on each clamp case's legal states, under a gap floor keeping every legal state below every illegal one. Constrained maximum likelihood with pruning and refitting fits terms from a fixed pool, and every delivered energy is audited exactly on all cases. Each energy is scored by time to a verified solution under restarts with its best of nine tuned samplers. In underdetermined modes, learned multipliers factor in 0.55, 0.44, 0.52 and 0.46 [0.38, 0.56] of the hand-written encodings' updates from 4x4 to 7x7, faster within every family below 7x7 at no resolved work penalty; learned adders solve the reverse mode in 0.71 of the updates at 8 bits and about a quarter at 24 and 32 bits, at 0.55 of the work at 32 bits. At 5x5 under equal pool, budget and floor, a gap-maximizing fit reaches 0.79 [0.73, 0.88] in updates and 1.26 in work against the hand-written encoding, while likelihood fitting takes 0.55 [0.46, 0.58] and 0.58 [0.48, 0.61] of the gap fit's updates and work. Rounding coefficients to the narrowest exact integer words tested, we run both energies at each pair's common word on one FPGA color-sweep SSA core, bit-exact with software: learned multipliers take 0.41 of the hand-written encoding's cycles at 4x4 and 0.057 [0.045, 0.068] at 7x7, at up to 2.4 times its lookup tables. The method requires only a circuit's legal assignments; in determined modes, hand-written encodings take less work, and from 12 bits on the adder fewer updates.