← 研踪 PaperTrailarXiv:2512.00053 · v4
Ten-Four: An Open-Source Fused Dot Product Unit for Mixed-Precision GPGPU Tensor Cores
首次提交 2025-11-19 23:57
版本更新 2026-11-09 09:54
雷达观测 2026-11-10 13:18
摘要
Efficient mixed-precision MMA operations are critical for accelerating deep learning workloads on GPGPUs. However, existing open-source GPGPU Tensor Cores rely on discrete arithmetic units causing high latency, accumulated rounding errors, and poor resource utilization. To address these challenges, we propose Ten-Four, a configurable mixed-precision fused dot product (FEDP) unit microarchitecture implemented as part of the open-source RISC-V Vortex GPGPU's Tensor Core Unit extension. It supports low-precision multiplication in TF32, FP16, BF16, FP8, BF8, INT8 and INT4 with FP32/INT32 accumulation, native OCP Microscaling (MX), and sparse lane clock-gating for dynamic power reduction, while matching NVIDIA Tensor Core numerical accuracy. Ten-Four achieves 4-cycle latency at 300 MHz on the AMD Alveo U55C FPGA, delivering 2.7--7.9 speedup over Berkeley HardFloat and FPnew at less than 60% the area cost. We further demonstrate its format extensibility by prototyping LNSF4, an NVFP4-variant matching its perplexity with 6.7% fewer LUTs and 11.1% lower dynamic power.
作者备注：13 pages, 12 figures, 6 tables
观测到的版本
相邻记录可能跳过中间版本；首次发现 v2 及以上也会标为版本更新。
v4 · 2026-11-09 09:54 · 最新观测版本
Ten-Four: An Open-Source Fused Dot Product Unit for Mixed-Precision GPGPU Tensor Cores
Efficient mixed-precision MMA operations are critical for accelerating deep learning workloads on GPGPUs. However, existing open-source GPGPU Tensor Cores rely on discrete arithmetic units causing high latency, accumulated rounding errors, and poor resource utilization. To address these challenges, we propose Ten-Four, a configurable mixed-precision fused dot product (FEDP) unit microarchitecture implemented as part of the open-source RISC-V Vortex GPGPU's Tensor Core Unit extension. It supports low-precision multiplication in TF32, FP16, BF16, FP8, BF8, INT8 and INT4 with FP32/INT32 accumulation, native OCP Microscaling (MX), and sparse lane clock-gating for dynamic power reduction, while matching NVIDIA Tensor Core numerical accuracy. Ten-Four achieves 4-cycle latency at 300 MHz on the AMD Alveo U55C FPGA, delivering 2.7--7.9 speedup over Berkeley HardFloat and FPnew at less than 60% the area cost. We further demonstrate its format extensibility by prototyping LNSF4, an NVFP4-variant matching its perplexity with 6.7% fewer LUTs and 11.1% lower dynamic power.
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