← 研踪 PaperTrailarXiv:2611.05704 · v1
Memory-Access Profiling for Early Multicore Interference Awareness in Embedded Systems
首次提交 2026-11-04 06:32
版本更新 2026-11-04 06:32
雷达观测 2026-11-05 10:08
摘要
Applications executing on different multicore processors may interfere through shared resources. Such interference can introduce execution-time variability and complicate system integration, especially when applications that behave predictably in isolation are co-scheduled. This paper presents a profiling framework for early multicore interference awareness. The proposed approach captures source-level memory-operation traces from C applications with limited source-code modification and combines them with architectural parameters of the target platform. The framework maps memory accesses to cache sets and memory blocks, generates cache-occupancy profiles and heatmaps, and evaluates pairwise interference risks through a progressive three-stage analysis. First, a coarse-grained screening step classifies applications according to their non-stack memory-access behavior. Second, a static multicore cache-profiling step identifies cache sets whose combined footprint exceeds or approaches the hardware associativity. Third, a temporal footprint analysis tracks intervening unique blocks between consecutive accesses to the same memory block and computes Contention Potential Growth to identify execution windows vulnerable to cache eviction. The framework is evaluated using four benchmark pairings executed on a dual-core platform, with hardware performance counters measuring L2 cache misses used as validation references. The results show that the proposed analysis is consistent with the observed high- and low-risk cases and provides conservative warnings for near-capacity configurations. In particular, different applications pairs might produces up to 213.09% increase in L2 cache misses. These results demonstrate that memory-access profiling can provide practical and interpretable early indicators of cache-related multicore interference before exhaustive hardware testing.
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v1 · 2026-11-04 06:32 · 最新观测版本
Memory-Access Profiling for Early Multicore Interference Awareness in Embedded Systems
Applications executing on different multicore processors may interfere through shared resources. Such interference can introduce execution-time variability and complicate system integration, especially when applications that behave predictably in isolation are co-scheduled. This paper presents a profiling framework for early multicore interference awareness. The proposed approach captures source-level memory-operation traces from C applications with limited source-code modification and combines them with architectural parameters of the target platform. The framework maps memory accesses to cache sets and memory blocks, generates cache-occupancy profiles and heatmaps, and evaluates pairwise interference risks through a progressive three-stage analysis. First, a coarse-grained screening step classifies applications according to their non-stack memory-access behavior. Second, a static multicore cache-profiling step identifies cache sets whose combined footprint exceeds or approaches the hardware associativity. Third, a temporal footprint analysis tracks intervening unique blocks between consecutive accesses to the same memory block and computes Contention Potential Growth to identify execution windows vulnerable to cache eviction. The framework is evaluated using four benchmark pairings executed on a dual-core platform, with hardware performance counters measuring L2 cache misses used as validation references. The results show that the proposed analysis is consistent with the observed high- and low-risk cases and provides conservative warnings for near-capacity configurations. In particular, different applications pairs might produces up to 213.09% increase in L2 cache misses. These results demonstrate that memory-access profiling can provide practical and interpretable early indicators of cache-related multicore interference before exhaustive hardware testing.
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