← 研踪 PaperTrailarXiv:2611.11475 · v1
CU-3D: A Scalable Legality-Aware RTL-to-GDS Flow for 3D-IC Physical Design
首次提交 2026-11-09 00:13
版本更新 2026-11-09 00:13
雷达观测 2026-11-10 12:16
摘要
Face-to-face (F2F) hybrid bonds shorten interdie connections, but data, clock, and power-grid (PG) connections must be realized together. CU-3D is a RTL-to-GDS physical design flow based on commercial EDA tools. It derives role-compatible hybrid-bond (HB) sites from a 17-metal ASAP7-based technology model, complete HB footprints, and constructed PG geometry. To coordinate partitioning with placement flexibility, Scaled refines an inherited 2D placement, whereas Fresh places the receiving die first and uses its pin locations and clock loads to guide placement of the other die. Data and clock HB assignments are jointly optimized while retaining alternative data sites and reserving capacity for subsequent PG assignment. The selected HB sites and stacks are preserved during 3D clock-tree synthesis, supply-aware cell insertion, and routing. Across eleven designs, including a 133-macro processor, the flow achieves zero backend DRC violations and passes signal-connectivity checks. Nine paired designs admit lower-footprint, lower-power implementations; four improve setup WNS. On JPEG, early joint planning gains 87 ps and mobility-aware partitioning gains 346 ps. Path analysis explains why cell-delay savings can outweigh net-delay increases.
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v1 · 2026-11-09 00:13 · 最新观测版本
CU-3D: A Scalable Legality-Aware RTL-to-GDS Flow for 3D-IC Physical Design
Face-to-face (F2F) hybrid bonds shorten interdie connections, but data, clock, and power-grid (PG) connections must be realized together. CU-3D is a RTL-to-GDS physical design flow based on commercial EDA tools. It derives role-compatible hybrid-bond (HB) sites from a 17-metal ASAP7-based technology model, complete HB footprints, and constructed PG geometry. To coordinate partitioning with placement flexibility, Scaled refines an inherited 2D placement, whereas Fresh places the receiving die first and uses its pin locations and clock loads to guide placement of the other die. Data and clock HB assignments are jointly optimized while retaining alternative data sites and reserving capacity for subsequent PG assignment. The selected HB sites and stacks are preserved during 3D clock-tree synthesis, supply-aware cell insertion, and routing. Across eleven designs, including a 133-macro processor, the flow achieves zero backend DRC violations and passes signal-connectivity checks. Nine paired designs admit lower-footprint, lower-power implementations; four improve setup WNS. On JPEG, early joint planning gains 87 ps and mobility-aware partitioning gains 346 ps. Path analysis explains why cell-delay savings can outweigh net-delay increases.
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