← 研踪 PaperTrailarXiv:2611.16202 · v1
An Agentic Python Framework for LLM-Driven UVM Testbench Synthesis with Closed-Loop Compiler Feedback
首次提交 2026-11-12 10:48
版本更新 2026-11-12 10:48
雷达观测 2026-11-13 14:16
摘要
Protocol bridge verification is a persistent bottleneck in SoC development: for every new bridge instance, engineers hand-craft a full UVM testbench from scratch, consuming 40--100 engineering hours of bring-up effort. We present an agentic Python framework that generates complete, protocol-aware UVM testbenches for arbitrary IP and subsystem configurations from a structured Verification Manifest---a JSON specification encoding interface topology, protocol semantics, and coverage intent. The framework employs a dual closed-loop architecture: an inner compiler feedback loop that injects categorised UVM diagnostics rather than raw tool output, and an outer coverage loop driven by intent-gap analysis against the Manifest. Validated on the AMBA AHB-to-APB bridge---a representative production protocol bridge with a 7-state control FSM, two-phase APB handshake, and non-trivial burst serialisation logic---the framework achieves 96.8% functional coverage, a bring-up speedup, and a Protocol Verification Completeness score of 0.87, with only 2.1% of the generated 4,623-line testbench requiring human correction. The generated scoreboard independently identified a critical RTL functional fault that the manual baseline missed entirely. Generalisation across four protocol families confirms that speedup increases with protocol complexity, ranging from (APB Subordinate) to (CHI Subordinate).
作者备注：Accepted at IEEE ISVLSI 2026, Kolkata, India. Copyright 2026 IEEE
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v1 · 2026-11-12 10:48 · 最新观测版本
An Agentic Python Framework for LLM-Driven UVM Testbench Synthesis with Closed-Loop Compiler Feedback
Protocol bridge verification is a persistent bottleneck in SoC development: for every new bridge instance, engineers hand-craft a full UVM testbench from scratch, consuming 40--100 engineering hours of bring-up effort. We present an agentic Python framework that generates complete, protocol-aware UVM testbenches for arbitrary IP and subsystem configurations from a structured Verification Manifest---a JSON specification encoding interface topology, protocol semantics, and coverage intent. The framework employs a dual closed-loop architecture: an inner compiler feedback loop that injects categorised UVM diagnostics rather than raw tool output, and an outer coverage loop driven by intent-gap analysis against the Manifest. Validated on the AMBA AHB-to-APB bridge---a representative production protocol bridge with a 7-state control FSM, two-phase APB handshake, and non-trivial burst serialisation logic---the framework achieves 96.8% functional coverage, a bring-up speedup, and a Protocol Verification Completeness score of 0.87, with only 2.1% of the generated 4,623-line testbench requiring human correction. The generated scoreboard independently identified a critical RTL functional fault that the manual baseline missed entirely. Generalisation across four protocol families confirms that speedup increases with protocol complexity, ranging from (APB Subordinate) to (CHI Subordinate).
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