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原文摘要

Rapid Single Flux Quantum (RSFQ) logic can operate at ultra-high clock frequencies; however, its physical design is complicated by explicit splitter trees and deep gate-level pipelines in which every logic gate is clocked. To address this challenge, we present qLevelPlace, a level-based placement framework for RSFQ circuits. We separate gate and splitter placement into two stages to better support levelguided gate-to-row assignment and use a timing-aware quadratic cost function to penalize long interconnects. Experiments on the benchmark circuits show that, on average, qLevelPlace achieves a $2.65\times$ higher clock frequency and a 51% reduction in layout area compared with the state-of-the-art RSFQ placer qPlace.